Data signals which have been generated with a certain shape tend to become distorted during propagation in electrical circuits. After having passed through one or more electrical circuits, the data signal is given a time sequence which more or less deviates from the time sequence it was given when it was generated. For binary data signals it is usual that the distortion appears, inter alia, in the form of pulse ratio changes and jitter. Distortion in data signals can be caused by band limitations, crosstalk, reflections and other physical imperfections or limitations in electrical equipment.
In systems where data signals are to propagate via a plurality of circuits and in certain other connections, the distortion can be so great that at one or more places it is necessary to restore the data signals so as not to risk that their capacity for carrying information shall be lost. There are several known methods and apparatus for more or less reconstructing or restoring data signals, particularly binary signals with data timing corresponding to a clock signal frequency.
An automatic phase correction circuit for phasing in a data signal relative to a clock signal is summarily described in the article "BROADBAND SWITCHING NETWORK AND TV SWITCHING NETWORK FOR 70 MBIT/S" by K. D. Langer, F. Lukanek, I. Vathke och and G. Walf, Heinrich-Hertz-Institut fur Nachrichtentechnik Berlin GmbH, 1000 Berlin, Federal Republic of Germany. The phase correction circuit includes a signal delay means, sensing means and a phase detector. The phase correction circuit is said to function in principle so that it switches in and switches out delay elements.
Apparatus for restoring a data signal and phasing it in relative a clock signal is described in "HIGH SPEED (140 MBIT/S) SWITCHING TECHNIQUES FOR BROADBAND COMMUNICATION", by D. Boettle and M. Klien, Standard Electric Lorenz AG (SEL), Research Center 7000 Stuttgart, Federal Republic of Germany. The apparatus includes an adjustable delay circuit connected for receiving and delaying the data signal which is to be restored. The apparatus also includes a phase detector connected for receving the clock signal and the delayed data signal. In addition, the apparatus includes control logic connected to the phase detector and delay line. The phase detector senses the delayed signal at three or five sensing times determined by the clock signal. The control logic changes the delay of the delay line stepwise in response to the result of this sensing. Each step is approximately 1 nS and the maximum delay of the delay line is approximately 7 nS, which approximately corresponds to one period of the clock signal at the frequency of 140 Mbit/s.